The present invention relates to a semiconductor device having a MOS transistor structure and a method of manufacturing the same.
With a recent increase in the integration density of semiconductor devices, miniaturization of the elements has been accelerated. However, with the miniaturization of the device, various problems have been raised. For example, when an MOS transistor is miniaturized, the junction depth of a source/drain diffusion layer is reduced, with the result that the sheet resistance of the source/drain diffusion layer rapidly increases and the operation rite thus significantly decreases.
To describe this problem more specifically, when a source/drain diffusion layer (0.2 .mu.m in depth) is formed by diffusing impurity ions in a concentration of 1.times.10.sup.20 cm.sup.-3, the sheet resistance becomes as large as 100 ohm/square or more. To solve the problem, a so-called SALICIDE (Self-aligned Silicide) technique has been intensively studied in recent years.
FIG. 1 is a cross sectional view of a conventional MOS transistor formed by the SALICIDE technique. The steps of manufacturing the MOS transistor will be explained below in the order of manufacturing. An element isolation film (SiO.sub.2 film) 801 is first formed selectively on a silicon substrate 800 by a well-known LOCOS method. Subsequently, a gate Insulation film 811, a gate electrode 802, an upper gate-insulation film 809, and a side wall gate-insulation film 810 are formed, and a shallow source/drain diffusion layer 803 (0.15 .mu.m in depth) is formed by ion implantation.
After a Ti film (30 nm) is deposited over the entire surface of the resultant structure by sputtering, the substrate is subjected to heat treatment called a rapid thermal annealing (RTA) in a nitrogen atmosphere for 30 seconds at 700.degree. C. As a result, a TiSi.sub.2 film 804 is formed between the source/drain diffusion layer 803 and the Ti film.
The Ti film remaining unreacted on an insulation film including the element isolation film 801 is selectively removed with a mixed solution of sulfuric acid and hydrogen peroxide. Subsequently, an interlayer insulation film (SiO.sub.2 film) 805 is formed over the entire surface of the resultant structure.
After a contact hole is made in the interlayer insulation film 805, a buried electrode 806, an upper electrode wiring layer 807, and an upper insulation film (SiO.sub.2 film)808 are formed. The MOS transistor is thereby manufactured.
As is described above, by virtue of the presence of the TiSi.sub.2 film 804 formed on the source/drain diffusion film 803, the source/drain region exhibits a sheet resistance of 5 ohm/square. This sheet resistance is 1/20 or less of the sheet resistance of the source/drain region in the absence of the TiSi.sub.2 film 804. Therefore, the formation of the TiSi.sub.2 film contributes to a decrease in the sheet resistance, ensuring the high speed operation of a miniaturized semiconductor device.
However, as the results of the intensive studies on the SALICIDE technique, the presence of the following problems have been confirmed. When the gate length becomes 0.2 .mu.m or less with the miniaturization, the depth of the source/drain diffusion layer must be set as shallow as 0.1 .mu.m or less, to suppress the short channel effect.
When the source/drain diffusion layer 803 is formed shallow, it is destroyed to increase a junction leakage. This is because Si is consumed when the source/drain diffusion layer 803 (Si) reacts with the Ti film to form an alloy (TiSi.sub.2) film 804.
To prevent an increase of the junction leakage, it is effective to reduce the Si consumption by reducing the thickness of TiSi.sub.2 film 804. If the Si consumption is reduced, the sheet resistance of the source/drain region inevitably increases, making it difficult to attain the anticipated object, an improvement of the operation rate.
The source/drain diffusion layer 803 is usually formed by ion implantation. For example, BF.sub.2.sup.+ ions are implanted at 10 keV in a dose of 8.times.10.sup.14 atoms/cm.sup.2 and subjected to heat treatment for 30 minutes at 900.degree. C. In this manner, the source/drain diffusion layer 803 can be formed with a depth of about 0.09 nm. The depth is defined as the distance from the surface of the substrate to a position where a boron concentration is 1.times.10.sup.17 atoms/cm.sup.3.
However, the ion implantation method has problems. There is a limitation in lowering the implantation speed. A profile changes at the time of implantation and activation of the ions. Hence, the shallow source/drain diffusion layer with a low resistance cannot be formed without limitation.
To deal with this problem, a technique has been recently proposed comprising the steps of absorbing an impurity such as boron in a substrate or depositing a thin film containing an impurity on a substrate, and diffusing the impurity into the substrate by a brief heat treatment performed at a high-temperature, thereby forming the shallow source/drain diffusion layer with a low resistance. However, this method requires a technique for adsorbing an impurity or depositing the impurity-containing thin film selectively to a desired region.
In the case of the ion implantation, impurity ions can be selectively injected only into a desired source/drain formation region by using a resist as a mask. However, it is extremely difficult to isolate and process the impurity-adsorbing region or an impurity-containing thin film formed on a gate electrode by use of the resist mask since the gate electrode is formed in the lowermost dimensions. In the regions other than the region on the gate electrode, a sufficient margin must be maintained to compensate for a lithographic misalignment relative to the proximity of the gate electrode, for example, to the source/drain region. Therefore, in the ion implantation method, techniques are also required for selectively absorbing an impurity and for selectively depositing a thin film.
As one of the selective deposition techniques, known is a technique for depositing the impurity-containing thin silicon film by thermally decomposing a mixed gas consisting of a source gas containing a silicon material (e.g. dichlorsilane or a silane gas) and an impurity-containing gas, (e.g. a di-borane gas).
However, such a selective deposition technique has the following problems:
Deposition must be performed at a relatively high temperature;
The deposited thin silicon film is epitaxially grown;
The gas used herein is limited in type; and
Gas-flow amount, temperature, atmosphere and the like defining the deposition selectivity are limited to narrow ranges.
The selective deposition technique is not an established technique as mentioned above and may therefore affect the reliability of the transistor characteristics.
To sum up, in the conventional SELICIDE technique, there is a problem in that a junction leakage increases as the junction depth of source/drain diffusion layer becomes shallow since the source/drain diffusion layer is destroyed due to the Si consumption of the source/drain diffusion layer at the time the silicide film is formed.
As one of techniques for forming a shallow source/drain diffusion layer except for the ion implantation, known is a method enabling selective depositing of an impurity-containing thin silicon film. However, this method is not suitable in practice because a process temperature is relatively high, the gas-flow amount, temperature, atmosphere, and the like are limited to narrow ranges.